There is a split in the SiC industry between IDMs who are opting for conservative, safe planar MOSFET designs, and those who are pushing ahead with efficent, compact, trench MOSFET designs. While the planar designs appear to have the majority of the booming electric vehicle drivetrain inverter market today, cost pressures and marginal gains may in the near future bring trench deisgns to the fore. In this article we explain the different pros and cons of the two designs, their current commercial implications and the future outlook for these devices.
Just as each of the major SiC IDMs have pursued their own strategy when it comes to their substrate supply, their expansion plans, and their customer bases, another major point of strategic difference lies in the way each company are designing their transistors. Until the end of 2023, there was a split between the “big 5” Western SiC device manufacturers, with STMicro, onsemi, and Wolfspeed having pursued traditional "Planar" MOSFET architectures, and Rohm and Infineon having developed more complex Trench MOSFET architectures.
At the end of 2023, at the International SiC Conference (ICSCRM) in Italy, notable divergent strategies were presented by onsemi and ST Micro regarding the future direction of their MOSFET designs. onsemi announced that their M4T MOSFETs released in 2024 would be their first generation of trench MOSFETs. By contrast, ST Micro committed to planar design devices for at least the next two generations of releases.
In this article, we shall dive into the relevance of the device design, attempting to put into some perspective the differences between these devices and their commercial implications. We shall first consider as background the role of device design for advancing the technology and lowering costs, before looking at the fundamental differences between the designs and the pros and cons of opting for one or the other. Finally, we shall look at the relative commercial success of the trench vs planar decision to date, before considering the outlook for the technologies over the next 5 years.
Background – Chip Design Trade offs
Device designers in each IDM play a critical role in determining the characteristics of their product. At their hands lie the critical trade-offs between the SiC chip size (and hence its cost), its efficiency (its resistance and switching losses), and its reliability and robustness.
We have written extensively in the past about the economics of device design. After the expensive boule growth, wafering, epitaxy, fabrication, and the losses associated with yield, a finished 150mm SiC wafer will have cost more than $1500 to produce. Therefore, given the cost embedded in a finished wafer, it is imperative to minimise the area of each MOSFET die, thereby maximising the number of die cut from each processed wafer.
The crucial parameter for a device designer is a MOSFET’s specific on-resistance (Ron.A), a measure of the resistance of a unit area of semiconductor, with units Ω.cm2. This value dictates how large a die will need to be to achieve a product of a given resistance. If the Ron.A of a MOSFET technology can be reduced, then the chip area of a fixed resistance product (e.g. a 15 mΩ MOSFET) can be minimised, thereby maximising the number of die cut from each wafer. Or, alternatively, where die size is a standard (e.g. a 5x5mm automotive die), so that die’s resistance will be minimised, reducing its losses. This is again more profitable for the IDM as a lower resistance product will have a price premium over a higher resistance product.
A second benefit of reducing die size (or maximising power density) is in minimising switching losses, energy that is wasted each time a device is switched on or off. Switching losses are a result of a device’s capacitance, which in turn scales linearly with die area.
Since the release of the first planar SiC MOSFET by Wolfspeed in 2011, there has been a steady reduction in Ron.A with each generation released, as shown in Figure 1. Today’s lowest Ron.A product available is the Gen 4 Rohm Trench MOSFET, the subject of a previous PGC Blog post. This reduction over time is one indication of how efficiency, yield and cost have all improved from conservative early designs.
Small, power dense SiC MOSFET die are therefore a good thing for efficiency, by minimising switching losses, and for maximising the number of devices per wafer. However, as power density scales up, the local temperature of operation within the chip also rises. This has a major impact on a die’s reliability and its ability to survive under fault or overload conditions. There is, therefore, an inherent trade off, which pits die shrinkage for the sake of efficiency and economics, against reliability.
Introducing Planar and Trench Designs
Cross sections of a planar and trench MOSFET layout are depicted in Figure 2. Simply, a trench MOSFET design is a more compact design compared to a traditional planar MOSFET. It is a design that enables the key metal-oxide-semiconductor (MOS) interface in a MOSFET to be vertically oriented rather than laterally oriented, which permits a more compact and lower resistance design. As described previously, the lower specific on-resistance (specific on-resistance, Ω.cm2) of the trench design results in smaller die, with the trade offs that this entails.
Depicted in Figure 3 is a representative cross section of a traditionally laid out planar MOSFET, as fabricated on a SiC substrate. This “unit cell” is just 6 µm wide but, as represented in the second image in Figure 3, it can be a millimetre or more in length in its third dimension. It is also one of hundreds connected in rows across the die. The unit cell is the device designer’s playground, containing two metal-oxide-semiconductor (MOS) channels that turn the device on and off, the drift region thick enough to support the required voltage, and the thick substrate that provides mechanical support. Each of these features contribute some resistance to the total.
Two of the largest resistances (the JFET resistance and the channel resistance) are located at the top surface of the MOSFET. The subject of numerous PhD theses and decades of SiC conferences, many processing technologies and design tricks have been employed to minimise each of these resistances. However, reducing a device’s cell pitch is one of the most effective ways of minimising these challenging resistances, as halving the cell pitch will double the number of channels per unit area, thereby halving the resistance of the JFET and channel regions.
Yet the ability to reduce cell pitch in a planar design is limited. As seen in Figure 3, two source contacts, two channel regions, and a JFET region are all implemented laterally along the surface of the wafer, thereby taking up critical space on the wafer. Despite this, the cell pitch of the latest generations of SiC planar MOSFET are reducing, with ST’s latest planar MOSFETs having a cell pitch below 5 µm.
The trick of the trench design, as seen in Figure 4, is to position the same source-channel-JFET construction along a vertical trench sidewall etched into the SiC surface. While more complex in its design and fabrication, the trench MOSFET permits a step change in cell pitch. For example, Rohm’s latest 4th Gen Trench MOSFETs have a cell pitch that is just 2 µm wide, 2.5-3x smaller than the latest generations of planar devices. As further represented in Figure 4, which contains benchmark comparisons of the planar devices of Figure 3, the result of the reduced cell pitch is an ability to shrink die area, which ultimately leads to more die being produced from a single substrate. According to data we keep on all the latest devices, the latest 4th Gen trench MOSFETs from Rohm are about 8-15% smaller in area at a given resistance rating than planar devices on the market.
The resistances associated with the drift region and substrate are mostly unaffected by the trench vs planar gate design. However, having 3x more current carrying channels (and JFET regions) per unit area reduces the resistance of these regions proportionally, the equivalent in a water analogy of having three water pipes in parallel instead of one. With the channel and JFET resistances accounting for around 25-35% of the Ron.A of a planar MOSFET (at 650V), this explains the relative die shrink.
In summary, there is a benefit to employing trench technology in lowering a device’s resistance, particularly the proportion originating from the SiC channel, which remains stubbornly high compared to silicon technology. The increased complexity of these designs is mitigated given the implementation of effective trench designs in silicon over the past two decades, with Infineon and ST and others having a legacy of producing Si trench MOSFET and IGBT technology.
Trench Designs – The Challenges
While a small trench MOSFET die and a relatively large planar MOSFET die may have the same electrical resistance, the more compact layout of the trench architecture in Figure 4 will result in more heat being generated per unit area. With thermal conductivity an inherent, unchangeable, property of the material, this leads to increased temperatures within the smaller trench MOSFET die. From another perspective, considering the die as a whole, the same amount of waste energy may be converted into heat within the device, but it is now crammed into a smaller die.
Higher temperatures within a die result in numerous issues. Of greatest importance is the reliability of the MOSFET, which will suffer if it runs hotter, affecting the long-term survivability of the gate oxide the most. Furthermore, electrical resistance increases with temperature, thereby choking off the amount of current that can pass through it.
These factors have interesting implications. PGC has extensive data that shows that the current rating that manufacturers are prepared to give their SiC products of a given on-resistance rating is coming down over time, as they get more power dense. For instance, 650V SiC MOSFETs in the 20-30mOhm range, in T0247 packaging were, only a generation of devices ago, commonly rated to over 90 amps. Today, the latest generations of 20-30mOhm, TO247, MOSFETs are rated to around 55 amps.
Another important metric is a device’s ‘robustness’, its ability to survive extreme fault conditions. Examples include short circuit faults or a cosmic ray strikes, where in both cases large currents and voltages are present in the device at the same time, resulting in large power spikes and localised heating. It is the case again that the relative robustness of a small area, power dense, chip will be reduced compared to a more conservative planar device.
Put simply, the more power dense the device, the more compromises must be made. This has been most evident in the evolution of the short circuit immunity of SiC MOSFETs. While Figure 1 detailed the incremental progress in Ron.A seen over the last decade, Figure 5 puts this into perspective against the amount of time these successive MOSFET generations can survive a short circuit fault for. Early generations could survive a short circuit fault for over 10 µs, a value inherited from silicon devices. However, this now down to less than 3 µs for some parts today. Shown in the graph and explained in our previous post, part of what made Rohm’s trench MOSFETs exceptional was their reduction in cell pitch to 2 µm, while an innovative gate design maintained an impressive short circuit immunity of over 5 µs.
The issues of trapped heat affects any power dense MOSFET. However, as trench MOSFETs are typically more power dense than planar devices many of these issues will affect trench MOSFETs more.
Another challenge related to trench MOSFETs is their complexity. Rule one of SiC MOSFET design is that its gate oxide must be protected from the high electric fields within the SiC drift region. This is inherent in the planar design, the p-body contacts forming a natural shield that pushes the peak of the electric field to the bottom of the JFET region.
Conversely, trenches sunk into the SiC surface push the gate further into the drift region where there could be very high electric fields. It is therefore imperative for each trench MOSFET design to make use of structures that will protect the gate oxide. These can be seen in the Rohm design in Figure 4, where deep P-pillar structures connected to the source contact will force the peak of the electric field deeper into the device.
A knock-on challenge is that many of the easiest and most obvious methods to protect the trench gate have been patented, restricting a new entrant’s freedom to operate. Innovative designs used to protect the gate oxide, such as those from Infineon and Rohm, are well patented, and new designs must circumnavigate these.
Trench vs Planar: Commercial Implications
Until recently, the major SiC IDMs that opted for Trench MOSFET designs were Rohm and Infineon. The other major players, notably Wolfspeed, ST Microelectronics and onsemi, have all opted for planar designs.
A recent graphic released by Yole details the relative success of each of these companies in attracting Design Wins from OEMs. A trend appears to correlate greater success in the lucrative drivetrain inverter business with the companies producing planar MOSFETs. Despite this, Infineon have had some success in this market, while Rohm and Infineon are both picking up business in the lower power on-board charger market.
The reason for this trend may be a matter for debate. However, context is important: the high power drivetrain inverter requires many, high current SiC MOSFETs (up to 48 100A die in the Tesla Model 3), and is critical in the safe long-term operation of the vehicle. It is also an application that continues today to be dominated by tried and tested silicon IGBTs. A switch to SiC remains a bold move.
In this author’s opinion, OEMs are weighing up which SiC device will be the first they adopt in what is a big leap for a conservative industry. Indeed, we have already seen with Tesla (see our previous article here), their considerable derating of ST’s SiC planar MOSFETs that they first adopted in the Model 3, these being backed off from their potential to ensure the long term survival of this nascent technology. Therefore, safety, in the form of long-term reliability and robustness, will hold weight against efficiency and die cost as being of primary importance. In this context, the potential for a Trench MOSFET to offer slight cost or efficiency gains over a planar SiC device that already delivers 99+% efficiency holds less weight for this most stressful application.
Yet in other applications, such as on-board chargers, data centres, industrial machines, air conditioning units, etc, there are numerous applications where the benefits of a trench MOSFET in terms of efficiency and cost may prevail. This explains the relative success of Infineon and Rohm who, despite the automotive design win graphic, have 32% of the SiC MOSFET market share, according to a recent report from McKinsey and Company.
Trench vs Planar: Future Outlook
Today, most silicon power MOSFETs and many IGBTs have trench gate architectures. This came about as marginal gains in efficiency and costs became evermore important to push silicon to its fundamental limit. While SiC MOSFETs are still today some distance away from their material limit, it is my belief that the market will move towards trench architectures in the coming years. This will be driven from within the IDMs as they push the boundaries of specific-on resistance reduction, driving yield improvement and cost reductions, while at the same time increasing efficiency.
While the drivetrain inverter market is a planar-dominated space today, as each manufacturer passes through their first generation of SiC inverters and has trusted on the road data of the efficiency and reliability of SiC, so the push for lower chip costs may win out over previous caution. This will make for an interesting competition between those IDMs who now dominate the automotive market with planar products, versus those who took a gamble and led on trench MOSFET development early.
Moving forward, we will likely see the current planar MOSFET IDMs adding trench products to their portfolio. By running both product lines, this would allow them to benefit from both the different markets each device architecture can access.
Indeed, onsemi look like they be the first company to run both, having announced at the 2023 ICSCRM conference that they would release an M4 1200V trench product in 2024 that will have a specific on-resistance 25% lower than their equivalent planar M3 technology. At the same conference, however, ST made the bold, opposite statement that they would be sticking by planar designs for at least their next two generations of devices. This leaves Wolfspeed, who run only planar designs today and who have not made an announcement either way about adopting trench designs in the future.
Finally, we expect to learn more in 2024 of Infineon’s second generation of trench MOSFETs. Expect to see an aggressive step forward in specific on-resistance reduction, maximising the benefits of their in-house trench expertise.