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  • Writer's picturePeter Gammon

A deep dive into Soitec's SiC Substrates


The case for adopting a silicon carbide (SiC) inverter in the drivetrain of an electric vehicle is compelling. On replacing a legacy Si-based inverter, the SiC solution will result in an efficiency boost of ~5%. This means that more power is being delivered to the motor rather than being wasted in the DC-AC power conversion process. While there is a cost to making this switch, this is paid back multiple times over by reducing 5% of the vehicle’s expensive, heavy, lithium batteries. As a result, car manufacturers the world over are developing SiC inverters and the demand has never been greater for silicon carbide (SiC) transistors (MOSFETs) and the crucial silicon carbide substrates themselves. According to a number of analysts, the SiC market was worth $1-2bn in 2022 and is growing at around 30% CAGR.

Yet there remain important questions concerning the future of this fledgling industry. Of greatest concern is the cost and supply of SiC substrates. Despite announcements from Wolfspeed, Coherent, and others of increased wafer supply in the near future, the availability of the material remains a challenging constraint for the industry causing long lead times and high costs.

Furthermore, Tesla, who originally triggered the SiC boom when they launched their 2017 Model 3, announced they will reduce the amount of SiC they use for future low cost, low power vehicles. This could be seen as a positive: this is ultimately an announcement that SiC MOSFETs will feature in a low power, mass produced EV, where SiC has been predominantly limited thus far to the higher power/luxury sectors. However, given the solution is rumoured to be a hybrid Si IGBT – SiC MOSFET solution (despite the value case for all SiC solutions), there remains a pressure from the automotive OEMs for SiC die costs to reduce. With PGC Consultancy and Exawatt cost analysis identifying the substrate as 40-50% of the finished die cost, it is the fundamental material where the biggest cost savings must be found.

Given the scarcity and cost of SiC substrates it is unsurprising that Soitec’s SmartSiC product is one of the subjects we at PGC Consultancy are asked to discuss most frequently, alongside Wolfspeed’s transition to 200mm, and the rise of Chinese players in the market. In this deep dive into Soitec's SmartSiC product, we set out to explain what it is, what its potential impact could be on device technology and costs, and what the key challenges are to their technology and operating model.

As with all PGC Consultancy Ltd articles, this is not a sponsored article and all statements herein are the sole opinion of the author. We would however like to thank Soitec for responding with detail to our questions.

With Soitec’s Capital Markets Day scheduled for June 8th 2023, please get in touch if you wish to know more about Soitec’s SmartSiC substrates, the merits and challenges of the technology, or the numbers behind this analysis.

An overview of Soitec’s SmartCut processes.

As their name betrays, Soitec’s origin is the silicon-on-insulator (SOI) industry. SOI substrates are used across the electronics industry, with applications including communications, sensors, RF and power ICs. Shown in Figure 1, a SOI substrate comprises a thin silicon device layer (ranging in thickness from a few 10s of nanometres to a few microns), a thick silicon substrate that provides mechanical support, and the silicon dioxide “buried oxide” which is an insulator that separates the two. Devices made in the thin top layer benefit from the isolation via optimisation techniques not possible on conventional bulk substrates. In the power electronics space, these advantages include the ability to isolate and integrate low and high voltage devices in close proximity, while the oxide prevents a leakage path downwards from a p-n junction, enabling lateral power devices to operate efficiently at temperatures beyond 200°C.

Given the parallel of the SmartSiC process to the original Smart Cut(TM) process, it is worth appreciating briefly the SOI manufacturing process, shown in Figure 1. The process, as originally described here in 1997, starts with two conventional Si substrates, one a base or ‘handle’ substrate, the second a ‘donor’ substrate, which will donate the thin device layer to the final SOI stack. First, the donor substrate is oxidised forming the buried oxide on its surface. Hydrogen is then implanted into the same surface of the donor substrate, the hydrogen atoms coming to rest a shallow distance beneath the oxide, equivalent to the device layer thickness. The donor wafer is then cleaned and flipped over, so its oxidised and hydrogen implanted surface can be brought into contact with the base substrate. A room temperature hydrophilic wafer bonding process temporarily fuses the two wafers, before an anneal causes the implanted hydrogen to expand, splitting the donor substrate such that the device layer and buried oxide remains on the handle substrate. After a high temperature anneal to make permanent the bond, a CMP polish finishes off the SOI wafer. The rest of the donor wafer that remains can be reused for the next SOI wafer after its surface has been smoothed by a CMP polish.

Soitec’s Smart CutTM process
Figure 1: Soitec’s Smart Cut(TM) process for producing SOI substrates. Source: Soitec

Soitec turn to Silicon Carbide

After more than two decades producing SOI substrates, Soitec announced in 2019 that they would apply their Smart Cut(TM) process to SiC, to produce “engineered substrates” that would address the “challenges related to supply, yield and cost of silicon carbide substrates”. Details of Soitec’s SmartSiC process emerged in 2021, while in 2022 Soitec and STMicroelectronics announced they were “co-operating”, with ST set to qualify the wafers within 18 months of the announcement.

What Soitec revealed was their SmartSiC substrates. These, in summary, comprise of a thin layer of monocrystalline SiC permanently bonded to a (relatively) low cost, highly doped, polycrystalline SiC handle substrate, possibly provided by Mersen or other manufacturers. An image of the SmartSiC substrate can be seen in Figure 2, alongside the manufacturing process. In a ‘smart’ bit of marketing, Soitec have reused their SOI graphic, substituting out the Si wafers for a monocrystalline SiC donor wafer and a polycrystalline SiC handle wafer. This helps draw the parallels to the Smart Cut(TM) process: a monocrystalline SiC wafer is implanted with a light element, presumably hydrogen, before being cleaned, flipped over, and bonded to the handle wafer. Two anneals, the first at lower temperature cracks the donor wafer, the second at higher temperature makes the bond permanent, thus leaving a SmartSiC substrate and the majority of a SiC substrate that can be polished and reused.

Soitec’s Smart Cut(TM) process for reusing single crystal SiC substrates.
Figure 2: Soitec’s Smart Cut(TM) process for reusing single crystal SiC substrates. Source: Soitec

In response to our questions, Soitec confirmed that it is the carbon face of the mono-SiC that is bonded to the handle wafer, ensuring that a SmartSiC surface is a mono-SiC Si face – the same as a conventional SiC substrate. The mono-SiC layer bonded to the poly-SiC surface, which we assume to be in the order of 1µm thick, should be a suitable seed layer for a conventional epitaxial layer to be grown on its surface, followed by device fabrication.

The potential benefits of SmartSiC SiC substrates

One of the most well-known advantages of employing the SmartSiC process is the potential to reuse a single mono-SiC wafer, at least 10x according to Soitec, which could help to solve the issues of SiC material supply currently widely suffered in the industry. However, Soitec appear keen to transmit the message that this doesn’t necessarily mean that their wafers will be cheap as a result.

Rather, Soitec consider they have a premium product, based on the advantage of their SmartSiC substrates, that they minimise the resistances related to the substrate. The impact they claim to have on the substrate would have a major impact on driving down total device resistance (Rds,on), which allows the production of die that are smaller for a given resistivity. As we have discussed previously, smaller die mean more are produced on every wafer and at a marginally improved yield, thereby reducing individual die costs and improving fab capacity.

To understand the potential substrate resistance improvements, it is worth reviewing its role in a SiC power device, such as the planar MOSFET in Figure 3. Power devices are arranged vertically, with the high voltage drain terminal situated on the backside of the substrate. This arrangement maximises the current density of the device, but it requires current to pass down through the thin drift region, then through the substrate before reaching the drain.

SiC MOSFET Cross-sections and resistances
Figure 3: Left, the resistances that make up the Rds,on of a planar MOSFET. Despite being thin, the drift region (Rdrift) contributes the largest resistance, followed by the channel (Rch), the thick substrate (Rsubs), the JFET region (RJFET) and the source/drain contacts (Rc). Right, a SmartSiC substrate has a very low Rsubs, but adds a small bonding interface resistance (Rbi).

As such, the substrate, which is the largest contributor to die cost and fairly resistive, plays almost no active role in the device. During front-end fabrication, the 350 µm substrate provides mechanical support to the 5-10 µm epitaxial device layer. After this however, it is thinned down to 100-180µm (depending on the manufacturer and the generation) before the drain metal contact is deposited, thereby minimising the substrate resistance contribution. In a 750V MOSFET, where the drift region is just 6-8 µm thick, the substrate will contribute up to 17% of the device’s total resistance.

When a conventional monocrystalline SiC substrate is grown via seeded sublimation, a fundamental trade off exists between crystal quality (low defect density) and doping density (low resistivity). As the substrate is required to be the foundation for the epitaxial growth to follow, the quality of the substrate cannot be compromised, and hence its resistance is relatively high (typically 15-25 mOhm-cm). The limited doping density of a substrate also adds a small contact resistance (Rc) between the substrate and the drain. On the contrary, when producing a poly-SiC substrate, its defect density is of no concern and hence its doping density can be pushed to the limit, minimising its resistance.

Previously, Soitec had been coy on revealing much regarding the specifications of their wafers, referring in marketing only to maximum values for their resistivities. However, recently, at CS International 2023 in Brussels, Soitec presented for the first time their substrates' “typical” values, shown in Figure 4. According to this, the typical poly-SiC resistivity is 2.5 mOhm-cm, with a bonding interface adding 10 µOhm-cm2 to the specific resistance. They also suggested that their high doping all but eliminates contact resistance, reducing it from 50-100 µOhm-cm2, down to 5 µOhm-cm2.

Soitec Infographic on SmartSiC substrate resitivity
Figure 4: Soitec presentation, first shown at CS International in Brussels 2023, that quantifies the typical resistance benefit of SmartSiC substrates. Source: Soitec.

The values Soitec claim for lowering backside contact resistivity originate from a 2022 presentation to ICSCRM (not yet in print). In this, they found that the contact resistivity of their SmartSiC substrates without laser annealing was 10x lower than the same contact to a standard monoSiC substrate with laser annealing. They suggest therefore that the laser annealing stage could be eliminated, removing one back-end fabrication cost.

Finally, in response to my questions, Soitec claimed they were able to achieve a flatter substrate, sharing data of low SFQR values compared to mono-SiC. While this will be helpful to the processing, potentially improving yields, its benefit is unquantifiable for the models herein.

Analysing the cost benefits of SmartSiC Substrates

Technoeconomic models co-created by PGC Consultancy and Exawatt translate improvements in device technology and the supply chain into the cost of the finished die. This cost captures the substrate, epitaxy and fabrication costs, factoring in yield related to defect densities (epi yield) and device fabrication (die yield). In this section, we apply the modelling to the Smart Cut(TM) wafers to assess their potential benefit. This model uses as its benchmark, a best-in class commercial 15 mOhm 750V trench SiC MOSFET, formed on a traditional mono-SiC substrate thinned to 140 µm. Against this benchmark, we model the same device implemented on a SmartSiC substrate, using Soitec’s typical substrate and contact resistivity values, presented in Fig.4.

Bar graphs detailing the impact of SmartSiC substrate resistivity on MOSFET resistance and cost
Figure 5: Benchmarking the impact on 750V MOSFET resistance and its die cost when employing SmartSiC substrates, using Soitec’s best case “typical” substrate resistivity values.

The result, using Soitec’s “typical” resistivity values, is that our 750V trench SiC MOSFET would have a total device resistance x area (Ron.A) reduction of 20%. Taking into account thermal effects when scaling die, this translates to a 9.1% smaller die size. The smaller die increases the number of die per wafer, and increases % yield. This, combined with a fabrication process with no laser annealling, mean the finished die costs reduce by 10.9%.

Were Soitec’s typical resistivity values to be verified, then these would be impressive reductions indeed. Bearing in mind Rohm’s Gen 4 MOSFET has a Ron.A that is ~40% lower than their Gen 3, a 20% reduction is akin to future Ron.A reductions in a single generational leap. Furthermore, this assumes that everything about the device remains identical. If, for example, the packaging were to improve generation on generation, the more efficient heat removal could drive down the die size further.

The impact of the smaller die has a compounded effect on profit margins for the IDM. A new generation of smaller die yields more devices per wafer, each of which cost less to produce than the previous generation. Were the die selling price to remain fixed, with the IDM passing none of the cost savings to the customer, their profit margins would increase substantially, by 29% in the 750V MOSFET case above. In a supply constrained market, the IDM may be able to rake all that profit margin; however, over time, as competition increases and the market becomes more price sensitive, this would allow the previous margin to be maintained, passing on cost reductions to the customer.

When applying the same analysis to 1200V MOSFETs, the impact of the substrate resistance is diluted, due to the thicker, lower doped drift region required to support the higher voltage. As a result, the SmartSiC substrates reduce the device's Ron.A by 14.2%, which equates to a die cost reduction of 8.4%. The increased profit, assuming the cost saving is not passed on to their customers, is 21%.

Soitec Business Model: Substrate supplier or equipment supplier?

The modelling in this article assumed that Soitec was acting as a material supplier to a customer, in the same way as Wolfspeed, Coherent or SICC. It also assumed that the substrate’s cost was no more than the average SiC substrate price. However, given the potential cost benefit to the customer of implementing their devices on a lower resistance, Soitec appear set to place a premium price tag on their substrates vis-à-vis their rivals. This is reinforced somewhat by questions as to just how cheap a poly-SiC substrate is relative to a mono-SiC substrate, before the additional layer transfer costs . On their release to the open market, their exact pricing relative to existing products will therefore be one to watch.

However, Soitec were keen to suggest an alternative model, that they could act as a technology licensing company, offering their SmartSiC process to customers as a toolbox in their fabs. The idea is that this could result in a vertically integrated IDM installing at least 10x fewer SiC crystal growth furnaces, instead installing the SmartSiC systems that could reuse their mono-SiC substrates, with the added benefit of the low resistance properties mentioned previously. For this to be possible, one would need to consider more than just the technical merits of the Soitec wafers, but also the financial trade-offs. The cost of installing the Soitec system, its capex costs, would need to be less than that of installing the crystal growth furnaces they would replace. It follows that the OPEX costs of running the SmartSiC system, would need to be lower than the alternative. In calculations we have made with the little public information available, the cost case for 150mm substrates appears viable if the 10x reuse multiplier holds true.

Soitec themselves suggest that there would be both CAPEX and OPEX savings in the substrate supply were this to be implemented.

Yield, Reliability Qualification and Fab Integration

The analysis in the previous sections set out the potential cost savings of using a low resistance SmartSiC substrate compared to a conventional SiC mono-SiC substrate from e.g. Wolfspeed, Coherent, SICC, etc – if everything else is equal. This caveat is important, as the complex manufacturing process detailed raises a number of questions that require answers before this can become a widely adopted substrate in the SiC supply chain.

Defect Density

The first question relates to defect densities within the mono-SiC layer, after the SmartSiC processing steps. Any increase in defects would have a negative effect on yield, thereby reducing the benefits previously outlined. At PGC, we felt certain that the complex process, of hydrogen implantation, bonding, splitting, high temperature annealing and polishing, could not be beneficial to the substrate; and yet, these are all fairly standard fabrication techniques that would be unlikely to generate defects (unlike epitaxy for example).

Soitec’s response was to point to their own 2021 conference paper to ICSCRM. In this paper, images taken after KOH etching of a donor and SmartSiC substrate pair reveal matching defect densities. This is good analysis, although the total area analysed in this paper was an area of just 1 × 1 mm. In time, the expansion of this technique to a full wafer, or better, the use of a high resolution X-ray diffraction imaging (XRDI) technique, to produce a full 3D defect map of the Smart Cut layer would be useful to prove the defect density over the whole wafer.


Forming power devices on a substrate that contains a bonded interface leads to an often-asked question: will this bond prove reliable in the face of thermal cycling lasting the duration of an EV’s lifetime? Again, Soitec have gone out their way to address this, engaging Fraunhofer IISB, Erlangen to perform power cycling testing. Presented at PCIM 2022, the team at Erlangen put a number of Schottky diodes through their paces, passing sufficient current through them to raise the temperature by 120K over 3 seconds, before letting them relax back over the following 9 seconds. They then proceeded to repeat this 565,000 times (79 days equiv), monitoring the diodes’ temperature to imply its thermal resistance. Over this time, no diodes failed in either a SmartSiC or a mono-SiC control set. Over time, the sintered contacts in all devices degrade raising the thermal resisatance, yet this rise was lower, on average, for the SmartSiC devices.

This was a very professional and independent study of merit, that leaves little doubt about the reliability of the SmartSiC bonding interface. In the fullness of time, benchmarked comparisons for another standard reliability metric, short circuit withstand time, would further validate this study.

Soitec’s black 150mm and 200mm SmartSiC substrates
Fig 6: Soitec’s black 150mm and 200mm SmartSiC substrates. Source: Soitec.

Opaque vs Transparent Substrates

A difference between conventional SiC substrates and SmartSiC substrates is their colour and transparency. Nitrogen doped mono-SiC 4H-SiC is distinct in being almost transparent, with a colour I am told is close to olivine. The obvious difference is that the poly-SiC is black and opaque, as seen in Fig 6. When asked about the impact of this change on fabrication equipment such as photolithography, now installed with optical sensors tuned for mono-SiC substrates, Soitec played down this issue, commenting that they work with customers to make the adjustments required. To us, it is clear that a line setup exclusively for one wafer type or the other will have no issue; switching between would require adjustments or recalibrations.

10x reuse of a single mono-SiC substrate

The question behind any value case for SmartSiC is the 10x reuse number. In response to a question on the robustness of the 10x number, Soitec stated this was “based on the analysis of more than 1500 SmartCut SiC substrates, leveraging the built up knowledge of more than 2 million SmartCut silicon wafers per year”.

It remains clear to us that if a SmartSiC system were to be rolled out in situ within an IDM, it would need to be clear that this yield were transferable.


A SiC substrate is a necessary evil in the development of SiC power devices. Essential as a seed layer for the epitaxial layers above, it adds a significant resistance to the final product, which can only be overcome by chip scaling. Hence, conventional SiC substrates are thinned to the limit of what is handleable, post fabrication.

The SmartSiC uses only a micron thin mono-SiC layer bonded to an ultra-low resistance polycrystalline SiC substrate. Relying solely on Soitec’s publicly declared substrate values, PGC Consultancy calculated that the SmartSiC substrate could reduce a 750V MOSFET’s total resistance by 20%, resulting in a 10.9% cost saving per 750V rated MOSFET die. Combining the cost saving with the higher yield, an increased profit of 29% is calculated, assuming an unchanging die price to the customer.

The second benefit of the SmartSiC concept is its potential to unblock clogged SiC supply chains, with one mono-SiC substrate being used in the development of ten SmartSiC substrates. Early on, many commentators took this to mean that Soitec might seek to undercut the price of others. However, it is now clear that these will in fact be premium wafers, owing to their ultra-low resistivity. Soitec have also opened the door to being more than a wafer supplier, the idea being that the installation of their process directly into the IDMs offers capex and opex savings by reducing by up to 10x the required furnace capacity.

Soitec also have an answer to commonly posed questions, making use of the SiC conferences to prove the resistivity, low defectivity and reliability of their substrates. Most notably, they worked with Fraunhofer to prove that the bonding interface was reliable when stressed with temperature cycling akin to that suffered in the field. On defects, they have shown on the micron scale that they add no new defects to the layer transferred to the SmartSiC, however future work to extend that to the full wafer would provide certainty of the macro trend. The opportunity for independent validation of these substrates would allay any remaining technical doubts regarding these questions.

On their business model, we also conclude that customers being offered the chance to install the SmartSiC system in-house would scrutinise the 10x reuse number to ensure that was viable in-house, as well as examining the costs to run the system and the costs of a poly-SiC supply.

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