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  • Writer's picturePeter Gammon

Taking Stock of SiC, Part 1: a review of SiC cost competitiveness and a roadmap to lower costs

The silicon carbide (SiC) industry is growing rapidly in support of the material’s promise to deliver efficient, high power, fast switching and compact power electronics solutions. Within the narrow but lucrative voltage window of commercialised SiC devices, from 600 to 1700 V, the system level gains offered by opting for a wide bandgap alternative to traditional Si products are becoming well recognised. Certainly, the high-end electric vehicle (EV) market agree, where Tesla, BYD and Lucid, have switched over to full SiC inverters already, while many large OEMs have a SiC inverter in development.

While little doubt remains about the benefits that SiC power devices deliver in terms of switching speed and hence overall system size and efficiency, questions remain about the upfront cost of SiC devices compared to legacy Si options. So, what is behind this high price? What can be done to drive down the price and how does the incremental improvement of the SiC MOSFET factor into that reduction? What might the cost of SiC be in 10 years?

Using models and projections developed by PGC Consultancy for customers from the financial and semiconductor sectors, I will look to give you some answers to these questions, and to give you our view as to where the SiC technology and cost will be a decade from now.

What’s behind the cost of SiC?

The single biggest cost contributor is the SiC substrate itself, and it is fairly safe to predict that it will remain so for some time to come...

As of Sept 2021, 100 amp discrete SiC MOSFETs (both 650V and 1200V) are retailing at almost exactly 3x the price of the equivalent rated Si IGBT. This despite the SiC device taking up 3-4x less space on a processed wafer.

The reasons for this large cost differential are multiple, but the single biggest contributor is the SiC substrate itself, and it is fairly safe to predict that it will remain so for some time to come, eclipsing contributions from epitaxy, fabrication and yield. This is because high quality Si wafers are produced via the Czochralski process, in which metres long Si boules are pulled from a vat of melted Si at 1500°C. By comparison the seeded sublimation process used to produce SiC is slow, requiring significant energy to enable the 2200°C growth process, while the final usable boule is no more than 25 mm in length. This puts into context the 30-50x greater cost of a SiC wafer compared to Si.

Other costs contribute to the higher price of SiC compared to Si, but are relatively minor compared to the substrate costs. These include the costs of epitaxy (growth of a high quality SiC device layer on the substrate surface) and device fabrication, both of which require higher temperatures and more expensive consumables than in Si power device processing.

The final cost driver is the yield, at each of the aforementioned stages. These costs account for the number of unusable wafers taken from boules, and the number written off post epitaxy and fabrication. The biggest factor affecting die yield, post fabrication, is the material quality, including both the number of device-killing defects that originate from the boule growth and epitaxy processes, but also those less obvious defects that affect long-term reliability. Another issue in the fabrication is the reliability of the MOSFET gate oxide.

Figure 1: The cost breakdown of a SiC MOSFET die, based on a best-in-class 2021 1200V/100A device produced on a 150mm substrate.

Shown in Figure 1 is the cost breakdown for a SiC MOSFET die, with the yield derived from a best-in-class 2021 commercial 1200V/100A device produced on a 150mm substrate. The two stacks approximate two different substrate supply models, comparing the majority that buy their substrates at market prices, to those companies that are vertically-integrated and hence can self-supply the substrates at cost.

Depreciation costs are significant in some cases, but vary from supplier to supplier and are not included in this model. Device packaging is a significant additional cost to add to this, however, this cost is no different to Si based devices. Furthermore, while early EV inverters have used TO247 packaged MOSFETs, in time, one would expect bare die to be supplied for bespoke inverter modules.

Reducing SiC Costs

The combined result of a number of effects will bring about a decline in the SiC price. We will detail each of these below.

Today, SiC devices are predominantly developed on 150mm diameter substrates, though an upgrade to 200mm substrates is expected from Wolfspeed and GT Advanced Technologies in the next 6-12 months. This will enable around 1.8x more devices to be produced from a single fabrication run and as such, the fabrication costs will be reduced. However, at least to begin with, we don’t expect that this size upgrade will bring about a significant reduction in the substrate fraction of the die cost, as proportionally more inputs to the sublimation process will be required to produce the larger area wafers. As seen in the transition from 100 to 150mm then, we predict the substrate cost will scale proportionally with area initially, but will drop away steadily as the technology matures and competition increases.

In fact, die taken from a 200mm wafer are highly likely to cost more than their 150mm counterparts, at least in the first couple of years. This is because the optimisation of a new wafer size is a significant challenge, and wafer yield (affected by the uniformity and bow of a wafer) epitaxy yield and the die yield could be affected. Again, using evidence from the transition from 100 to 150mm, the density of both defects leapt up, at least initially and evidence of this is still out there if you know where to look: SKSiltron’s SiC page details the 100-200% increase in defects of all types from this previous transition. After a short period of development, 200mm defect density is likely to reduce, as is their cost of production; until then, 150mm wafers may well remain the cheaper solution, and it is reasonable to expect a tapered transition between these wafer diameters in the first few years.

The move to 200mm brings about a requirement for new, modern fab facilities, Wolfspeed’s impressive sounding Mohawk Valley Fab being a prime example. This will result in a much greater degree of automation, substantially reducing the number of highly skilled (e.g. expensive) engineers needed to run the facility, and reducing the fabrication costs. However, in the short term, expect that depreciation costs will increase, arising from the significant outlay.

The Self-Supply of substrates within 'vertically integrated' companies has a large affect on price. This is demonstrated in Figure 1, in which the cost of a substrate has been discounted by the sellers margin, presumed here to be 40%. This impacts upon the yield costs, as well as the the materials costs, because all the material written off is worth 40% less. As very few chip manufacturers are capable of universal substrate self-supply, this gives a competitive advantage to those who can.

Competition may force a downward pressure on price. onsemi's recent purchase of GTAT shows that consolidation in this field is not yet over, with a few small companies, with significant IP, still independent of the large companies making most of the running. Furthermore, China is ramping up its interest in SiC, as publicised recently. However, this is not the PV market and it isn’t possible to flood the market with cheap, low quality material. Instead, for any new entrant, it will take time to achieve the mature crystal quality, and device consistency demanded by the automotive industry and others.

Finally, and very importantly, the SiC device technology will improve. In particular, advances in the device design and processing will continue to reduce the resistance of a SiC MOSFET with each new generation released. Ohms law (I=V/R) dictates that any reduction in unit area resistance (Ron,sp; Ω.cm2) brings about an increase in current density (A/cm2). This means that the die area can be reduced while maintaining a given current rating. However, the problem of removing waste heat from a smaller die means that the change in thermal resistance (k) cannot be ignored, and hence chip area scales proportionally to the square root of both its electrical and thermal resistances (A∝√(R×k)) [1]. Hence, a 50% reduction in resistance would result in a 29% reduction in the active area of the die. Inactive areas (gate pads and termination for instance) will not scale to the same degree.

As an extra bonus, a smaller die size not only boosts the number of die per wafer, it also results in a greater percentage yield.

Each new generation of SiC products to date has seen its areal resistance, its specific on-resistance, reduce compared to the last. According to Wolfspeed, here, this reduction was around 40% each time.

SiC Cost Forecast

Selected, normalised results from the PGC Consultancy SiC cost forecast model are shown in Figure 2. More important than attempting to exactly predict the future device cost, this is an exercise in identifying which of the previously identified cost drivers may play the biggest role in driving down the costs. This has been an exercise in reality checking the impact of 200mm, versus that of continual device design improvement.

Three of the inputs to the cost model are shown, and the predicted output, all of which are normalised to known or estimated 150mm values in 2022.

Figure 2: The PGC Consultancy SiC cost forecast model, based on a best-in-class 2021 1200V/100A device. Above, threeof the inputs used in the model. Below, the projected die cost. All data is normalised to known or estimated 150mm values in 2022. The upper and lower bounds represent our best/worst case scenarios.

The model inputs. Three key inputs to the model are shown. Projections of the substrate cost are key, given its dominance of the total costs. Our base prediction is that the unit area cost of 200mm substrates will be slightly greater than for 150mm, but will drop at a faster annual rate than 150mm, as occurred in the 100/150mm transition.

An increase in defect densities – impacting epi yield – seems inevitable, and again history bares this out in the 100/150mm transition. How high they jump and how fast they decline is debatable. Not shown, die yield might be expected to follow a similar trend, as new processes are brought online and incrementally improved.

The final input is the die size, a value that affects both wafer sizes equally and dictated by how much the resistance falls in each new MOSFET generation. Two new generations (Gens 4 and 5) are modelled as arriving in 2022 and 2027, each generation responsible for a 45% reduction in resistance in the baseline scenario, 40% worst case, 50% best case. As discussed earlier, with area declining proportionally to the square root of resistance, the 40-50% reductions in resistance result in a 23-29% reduction in only the active area of the device. The initial die size is based on a best in class (as per Sept 2021) 1200V/100A MOSFET.

The output shown is the projected cost of a 1200V/100A MOSFET die from 200mm and 150mm substrates, with baseline, best case and worst case scenarios shown.


The cost of a 1200V/100A MOSFET die made on a 200mm substrate in 2030 could be 54% less than the cost in 2022, from a 150mm substrate

With the assumptions made, the model suggests that the cost of a 1200V/100A MOSFET die made on a 200mm substrate in 2030 could be 54% less than the cost in 2022, from a 150mm substrate. This improves to a 57% reduction best case, 50% in the worst case. The retail price of a 1200V, 100A IGBT is today 3x cheaper than an equivalent rated SiC MOSFET and, while the Si IGBT price will not be static over this timeframe, a decline in the SiC costs anywhere in the ballpark of our model will make the margin to Si much narrower.

Our next conclusion is that a move to 200mm substrates is unlikely to radically drop the SiC cost immediately. In fact, in every scenario we run, there is likely to be a premium to pay for using 200mm substrates initially, until the wafer yield and die yield begin to return to 150mm levels. However, it may only take a couple of years for the 200mm die cost to reach parity with 150mm, before the benefits of the larger substrates win through.

We could be being too negative here in our baseline scenario. Perhaps the extensive in-house trials on-going since 200mm substrates were first demonstrated in 2015 will prevent the same leaps in defect densities previously seen in the 100/150mm transition. Wolfspeed are bullish that this is true in their case, while they have run a pilot line to establish an early 200mm fabrication process. Our best-case scenario for 200mm wafers covers this possibility, with the die cost roughly equal to 150 mm on launch, before 200mm becomes cheaper in proceeding years.

Regardless of the initial state of 200mm, by 2030, when our models have evened out the disparities between the different diameter substrates, the full impact of the 1.8x area difference between the substrates can be estimated. Our baseline scenario suggests that a die from a 200mm substrate will be 31% cheaper compared to a die from a 150mm substrate.

Figure 3: A breakdown of the costs that contribute to the total projected 150 and 200 mm die costs, as per the baseline SiC die cost forecast model.

In our scenarios, the impact of the substrate diameter upgrade on cost is comparable to the impact of the improving technology. The two generations of device improvement in ten years are responsible for lowering the die cost by 27%, +/- 2.5% for the best/worst case scenarios. Hence, the continued marginal performance gains that device designers extract from innovations such as wafer thinning, trench architectures, or reducing node size, will be of fundamental importance for achieving the reduction in costs.

In Figure 3, the baseline results are further expanded to include their year-on-year contributions. The negative effect of yield on the early 200mm wafers can be seen, with this being a major portion early in their adoption. By 2030, the lower fabrication costs per die of the larger 200 mm substrates are fully evident in the data.


Increasing the cost competitiveness of SiC is an industry wide priority, yet there is no overnight solution to this. The introduction of 200mm wafers will help significantly in the long run, allowing the fabrication portion of the costs to be shared by up to 1.8x more devices, however, the substrates may need some time to reach the quality and yield values currently possible on 150mm. Our modelling demonstrates that the incremental improvement of the technology, generation to generation, is equally important. Lower resistance translates to smaller device area boosting the number of devices per substrate and the ultimate die yield.

Even in our most conservative predictions, the combined effects of adopting 200mm substrates, and two generations of device improvement, suggest that the costs that make up a SiC MOSFET will be half what they are today by 2030. With a 3x cost differential to make up to equivalent rated Si IGBTs, this would be positive.

In Part 2 of the Taking Stock of SiC series, we shall analyse the resistance components of a current SiC MOSFETs and examine where future savings may be made.


[1] W.J. Sung and B.J. Baliga, Design and Economic Considerations to Achieve the Price Parity of SiC MOSFETs with Silicon IGBTs, MSF 858, 889–893, 2016.

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