top of page
  • Writer's picturePeter Gammon

ST's first 200 mm SiC wafers

I am launching my blog page today, a fortnight after STMicroelectronics announced that they produced their first or 200 mm diameter SiC substrates. Good news, without a doubt, but it is an announcement that needs context, and perhaps shines a light on the lack of competition in the SiC materials market.

This announcement has been a subject of some interest in the SiC Community. SiC power devices, which are increasingly being adopted by electric vehicle manufacturers, are predominantly made on wafers that are 150 mm in diameter. A move to 200 mm wafers represents one of the biggest remaining steps forward in the commercialisation of SiC.

ST's first 200mm wafer. Source: STMicroelectronics

Fabrication on 200 mm wafers would result in around a 1.8x increase in the number of power device chips being produced in a single fabrication run. Furthermore, 200 mm is a wafer size often used to produce Si power devices, meaning that there is greater possibility of integrating SiC processes in Si lines.

ST’s announcement is great news then, and welcomed universally, as the SiC materials market is in desperate need of increased competition to lower price and ensure second (or third...) sources of supply. I have no wish to caveat that positivity too much – but it is an announcement that requires context.

Cree/Wolfspeed and II-VI were the first companies to demonstrate conductive 200 mm wafers, both in 2015. I write this not only to point out ST’s mildly irksome and tricksy press release title, but also to suggest that an announcement like this comes quite some time before chips made from 200mm SiC wafers are rolling out of a ST fab.

Six years on from these initial 200 mm demonstrator wafers, no company are openly selling or using 200 mm SiC wafers. Cree, who dominate the SiC material market, appear positive. They announced this year that they will be running 200 mm wafers in their new Mohawk Valley Fab when that is brought online in 2022. II-VI sell semi-insulating grade 200 mm SiC wafers but these do not require the ultra-low defect densities of conductive substrates. Relative new boys to the market, GT Advanced Technology, claim to be working toward 200 mm in early 2022.

ST plan to ‘source over 40% of its SiC substrates internally by 2024’.

The reason for this 6-year-and-counting delay, is that it is one (really tricky) thing, to make a SiC ingot at a new wafer diameter in the first place; but it is quite another to have a SiC wafer ready for production. The initial milestone of achieving that first ingot allows a press release, or to hold up a wafer on a conference stage – and at the macro level it will look like any other SiC wafer. It certainly serves to alert the world that they are coming. However, in reality, it takes countless cycles of improvement to the process, to the fundamental seed crystal, to the growth processes, until the number of microscopic defects (or crystal imperfections) are low enough to support adequate device performance.

For context, the transition from 150 to 200 mm will be the second step up in the last ten years, the fourth (possibly the fifth) in the last twenty years. On the last occasion, the 150 mm wafers that were initially released had defect densities much greater than the 100 mm wafers they were replacing. This legacy still lives on today, if you study the specifications of the two wafers side-by-side. So, even after launch, it takes time for that generation of wafers to improve.

This announcement by ST is a positive first step then, a proverbial wafer on the stage, but ST may still be some years from being 200 mm self-sufficient. This is reflected in the closing statement that ST plan to ‘source over 40% of its SiC substrates internally by 2024’. I think that this statement underscores how dependent the booming SiC chip industry is today on a very limited number of materials suppliers.

512 views0 comments

Recent Posts

See All


bottom of page